High-Level Synthesis for Real-Time Digital Signal Processing

1 Introduction. - 1. 1 History and related work. - 1. 2 Design methodologies for silicon compilation. - 1. 3 Design methodologies for architecture synthesis. - 1. 4 The cathedral silicon compilers. - 1. 5 Outline of this book. - 2 DSP architecture synthesis. - 2. 1 Digital signal processing. - 2. 2 DSP system specifications. - 2. 3 DSP target architectures. - 2. 4 Building a DSP silicon compiler. - 2. 5 Summary. - 3 Implementation of data structures. - 3. 1 Literature survey. - 3. 2 Memory management strategy. - 3. 3 Constrained storage. - 3. 4 Unconstrained storage. - 3. 5 Selecting resource types and instances. - 3. 6 Organising indirectly-addressed memories. - 3. 7 Organising directly-addressed memories. - 3. 8 Physical address generation. - 3. 9 Summary. - 4 Implementation of high-level operations. - 4. 1 Code expansion strategy. - 4. 2 Explicitising data dependencies. - 4. 3 Code expansion. - 4. 4 Data routing. - 4. 5 Summary. - 5 Implementation of control functions. - 5. 1 Literature survey. - 5. 2 Control function implementation strategy. - 5. 3 Selection. - 5. 4 Repetition. - 5. 5 Hierarchy. - 5. 6 Multi-rate systems. - 5. 7 Summary. - 6 Scheduling. - 6. 1 Scheduling strategy. - 6. 2 Scheduling algorithms. - 6. 3 Graph transformations. - 6. 4 The balancer. - 6. 5 Estimators. - 6. 6 Summary. - 7 Structure generation. - 7. 1 Literature survey. - 7. 2 Structure generation strategy. - 7. 3 Instance assignment. - 7. 4 Netlist generation. - 7. 5 Execution unit parameters. - 7. 6 Summary. - 8 Demonstrator designs. - 8. 1 An 8-ary baseband PAM modem for ISDN. - 8. 2 An 800 bit/s voice coder. - 8. 3 Summary. Language: English